Additional Responsibilities

• Logic Synthesis
• Hand-off to and from DFT
• Qualifying Libraries and Timing Constraints
• Design Partitioning and Floor Planning
• I/O Pad Ring Design
• Placement, CTS, Routing
• Power grid, Clock tree, and Low-power reduction Implementation methods
• Signal integrity fixes with OCV/AOCV/Statistical Timing methods
• IR drop analysis
• Physical Verification
• Functional and Timing ECOs
• Conformal Equivalence Check
• Conformal Lower Power (CLP)
• Timing Closure in Advanced Technology Nodes
• Multi-mode & Multi-corner (MMMC)Timing closure methodology implementation and sign off
• Experience with low power implementation, multi-Vt, power gating, multiple voltage rails, UPF/CPF knowledge
• Work closely with analog design team and IP vendors for physical implementation/integration of custom analog blocks/interface/IP’s

Qualifications

• 7+ years(preferred) of Physical Digital Design experience.
• Degree in Electrical Engineering/Computer Science or equivalent
• Expertise in programming, scripting and automation languages for PD flow implementation
• Strong technical abilities & understanding in these areas:
• Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners.
• Multipower domain, signal integrity, & power/IR drop analysis
• Linting, DFT and CDC requirements.
• Expertise in both hand-written and tool-driven functional/timing ECO.
• Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
• Experience with the following is desired:
• SOC design including uC design (ARM)
• Knowledge of power management industry/applications
• I/F: I2C, SPI, USB, SDC, ETH, etc.
• Multiple tapeouts and working silicon; in leading-edge technology node
• Proven track record demonstrating the ability to meet project milestones and deadlines
• Strong communication and interpersonal skills required to work with global design team
• Successful track record of leading a team of physical design engineers from RTL-to-GDSII