Your LinkedIn profile, personal website, or project portfolio
*
How many years of hands-on experience do you have in ASIC/SoC design?
*
How would you rate your proficiency in Verilog or SystemVerilog for RTL design?
*
Beginner — limited exposure
Intermediate — implemented modules under guidance
Advanced — independently developed complex RTL for multiple IPs/SoCs
Which of the following EDA tools have you used extensively? Select all that apply.
*
Synopsys
Cadence
Siemens
Others
Describe your experience with logic synthesis, timing analysis, and timing closure. Include any tools used and scope of responsibility.
*
Describe your experience with low-power design techniques, including UPF/CPF implementation or power integrity considerations. What approaches or tools have you used, and what challenges have you addressed?
*
Are you currently based in Singapore or eligible to work in Singapore?
*
Yes
No
Are you proficient in Mandarin/Chinese (spoken and written)?
*
Yes
No
Please indicate your annual salary expectations (in Singapore Dollars) for this role.
*
If successfully selected, how many days would you need in order to join?
*
Yes, Leapstrides Consulting FZ-LLC can contact me about job opportunities.
I may receive emails from leapstrides.com. I can opt-out at any time by unsubscribing or texting STOP. My data will be handled in accordance with
the privacy policy
and
Terms of Service
. For help, email
support@loxo.co
.
Powered by