We’re looking for hardware engineers with hands-on experience in chip design workflows—ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading EDA vendors such as Synopsys or Cadence. Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML workflows will stand out.

Responsibilities

• Drive direction and technical leadership across our multi-agent platform and domain-specific hardware knowledge base.
• Bring a deep understanding of chip design workflows and help shape product roadmap with real-world context.
• Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages.
• Track evolving trends in both semiconductor design and AI-assisted design automation.
• Create internal benchmarks and datasets to rigorously evaluate system performance across RTL, PD, and architectural use cases.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline (interns may be considered for their flair).
• Hands-on experience in a semiconductor or EDA environment (e.g., NVIDIA, AMD, Intel, Synopsys, Cadence), 1+ years of full-time experience required, 3+ years preferred.
• Proficiency in scripting (Python, Bash) and experience with automation or tooling for design verification or integration.

SPECIALTY: DI (Design Integration, RTL, Architecture)

• Proven track record of developing architectures and RTL for hardware blocks or IP.
• Experience with SystemVerilog, Verilog & SoC design methodologies.

SPECIALTY: PD (Physical Design)

• Part of leading edge tapeouts (7nm or smaller). Worked on at least one of synthesis, floor planning, place-and-route, physical verification, and timing.
• Familiar with one of Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler, or other relevant EDA CAD tool (and associated TCL).

Preferred Experience

• Experience on AI-for-chip-design initiatives (e.g., at Synopsys, NVIDIA, GoogleDeepMind).
• Understanding of DFT, power optimization techniques, or low-power design flows.
• Experience on an IP development team, developing PCIe, PHY, LPDOR, MemoryControllers, NoC, CPU subsystems, or similar.