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ASIC Engineer
USA
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ASIC Engineer

Location: Remote (United States) or Onsite/Hybrid (Client Dependent)

Employment Type: Contract or Full-Time (W2 Only)


Staffing Solutions United (SSU) is seeking an experienced ASIC Engineer to support advanced semiconductor development initiatives across high-performance and low-power silicon programs. This role requires strong expertise across digital design, integration, and implementation, with the ability to collaborate effectively in cross-functional engineering environments.

The ideal candidate will have hands-on experience across multiple stages of the ASIC development lifecycle, from architecture and RTL development through synthesis, timing closure, and silicon validation.


Key Responsibilities

  • Develop and maintain RTL designs using Verilog/SystemVerilog
  • Support microarchitecture definition and technical design documentation
  • Perform synthesis, constraint development, and static timing analysis
  • Contribute to power optimization and low-power implementation strategies
  • Collaborate with verification teams to ensure robust test coverage and issue resolution
  • Work closely with physical design teams on floorplanning, timing closure, and signoff
  • Analyze and optimize power, performance, and area (PPA) metrics
  • Participate in design reviews and maintain high engineering quality standards


Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline
  • 4+ years of ASIC or digital IC development experience
  • Strong proficiency in Verilog/SystemVerilog
  • Experience with synthesis and static timing analysis tools
  • Understanding of clock domain crossing (CDC) and reset domain crossing (RDC) methodologies
  • Familiarity with advanced technology nodes (28nm and below preferred)
  • Solid knowledge of digital logic design fundamentals


Preferred Qualifications

  • Experience with SoC integration and subsystem-level design
  • Familiarity with industry-standard EDA tools (Synopsys, Cadence, or equivalent)
  • Experience with low-power design techniques and UPF
  • Scripting experience (Python, Tcl, Perl) for automation
  • Exposure to DFT methodologies and silicon bring-up


Additional Information

  • Remote opportunities available depending on client program requirements
  • W2 engagement; no third-party or C2C arrangements
  • Candidates will undergo technical screening and verification


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