ASIC Design Engineer

Location: Remote (United States) or Onsite/Hybrid (Client Dependent)

Employment Type: Contract or Full-Time (W2 Only)

Staffing Solutions United (SSU) is seeking a highly skilled ASIC Design Engineer to support advanced silicon development programs across cutting-edge semiconductor initiatives. This role requires deep technical expertise in digital design, RTL development, and ASIC implementation within advanced process nodes.

The ideal candidate will have experience working across the full ASIC design lifecycle and demonstrate the ability to collaborate effectively with verification, physical design, and architecture teams to deliver high-performance, low-power silicon solutions.

Key Responsibilities

• Develop high-quality RTL code using Verilog/SystemVerilog
• Contribute to microarchitecture definition and detailed design specifications
• Participate in the full ASIC development lifecycle from concept through tape-out
• Collaborate with verification teams to ensure robust functional coverage and bug resolution
• Support synthesis, timing closure, and low-power implementation strategies
• Analyze and optimize performance, area, and power (PPA) metrics
• Work closely with physical design teams during implementation and signoff
• Participate in design reviews and maintain documentation aligned with engineering standards

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in ASIC or digital IC design
• Strong expertise in RTL design using Verilog/SystemVerilog
• Experience with synthesis tools and static timing analysis
• Familiarity with low-power design techniques (clock gating, power domains, UPF)
• Experience with advanced technology nodes (16nm and below preferred)
• Solid understanding of digital design fundamentals and microarchitecture concepts

Preferred Qualifications

• Experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes)
• Familiarity with scripting languages such as Python, Perl, or Tcl
• Experience in SoC integration and multi-clock domain designs
• Knowledge of DFT concepts and design-for-test methodologies
• Experience supporting silicon bring-up and post-silicon validation



Additional Information

• Remote opportunities available depending on program requirements
• W2 engagement; no third-party or C2C arrangements
• Candidates will undergo technical screening and verification